Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device

Authors

  • Marek Zielinsk
  • Maciej Gurski
  • Dariusz Chaberski

DOI:

https://doi.org/10.5821/iwp.2013.14.15432

Issue

No. 14 (2013)

Section

Articles

License

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